In practically all automatic general purpose digital computers, problems are solved by executing a number of instruction words comprising the computer program. An instruction word is a combination of binary digits (bits) which define the arithmetic or logical operation to be performed and also the addresses at which operands to be manipulated are stored. The portion of the instruction word defining the operation to be performed is commonly called the "operation code" or op. code. The number of discrete operations that can be performed by given computer is a matter of design choice and in prior art computers there may be as few as five instructions for small special purpose computers or more than one hundred for larger, more expensive, general purpose systems.
It is only by sheer coincidence that the number of instructions included in the instruction repertoire of a machine is a number equal to an integral power of two. Hence, the number of bits comprising the op. code portion of an instruction word will often define more binary combinations than are needed to define the valid instructions that may be carried out by the computer. For example, if a machine is designed to execute 140 distinct instructions, the op. code would have to include eight bits since the number 140 is in the range 2.sup.7 &lt;140&lt;2.sup.8. With 2.sup.8 bits, however, there are 256 possible combinations so that of this number there would be 116 possible invalid codes.
It is desirable that means be provided for detecting when an invalid code is present in the computer's instruction register and for generating an error interrupt signal so that proper remedial action may be taken. In prior art systems, such as described at column 31 of the Cheney et al U.S. Pat. No. 3,266,020, a rather complex instruction code translator is provided for decoding all of the instruction code bits and the outputs from the translator defining invalid codes are OR'ed together to produce the requisite error interrupt signal. Such a translator requires a multiplicity of logic circuits, adding to the cost of the computer and oftentimes slowing down the instruction execution rate.
To obviate this problem, the present invention provides a so-called "read-only" memory (ROM) connected to the instruction register of the computer such that the op. code bits are interpreted as addresses. Stored at each address in the ROM corresponding to an invalid instruction code is a logical "0" signal while a logical "1" signal is stored at each address corresponding to a valid instruction code. Hence, each time a new instruction word is entered into the instruction register, a "1" or a "0" signal, hereinafter referred to sometimes as a "flag" bit, will be read out from the ROM and thereby indicate whether the op. code is valid or invalid, respectively.